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PLLs AND CLOCK RECOVERY
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Basic Concepts of PLL Topologies
Basic definitions and concepts of phase locked loop topologies. Frequency behavior, stability and settling of PLL topologies. Introduction of fractional N synthesizers. |
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CMOS Prescalers & Advanced Loop Filters
High-speed CMOS prescaler, dual modulus prescaler and advanced circuit techniques, such as phase switching architectures, are discussed in detail. The limitations and requirements of the phase detector and loop filter towards fully integrated PLL synthesizers are discussed. A case study of an integrated synthesizer for DCS1800 applications is analyzed. |
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Integrated VCOs and Synthesizers
Fundamentals and principles of VCO circuits. Lay-out and design issues of spiral inductors and varactors for CMOS VCO circuits. Effect of loop filter and VCO noise on phase noise behavior of PLL synthesizers. design examples of fully integrated synthesizers in CMOS technologies. |
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Modeling and Design of High-Speed VCOs
In this module we will discuss modeling of phase noise in VCOs. We will start by introducing the time-varying response of oscillators and using the impulse sensitivity functions describes various noise conversion mechanisms in oscillators. In particular we should how low frequency noise and correlated and uncorrelated supply and substrate noise can convert to phase noise and how the time varying properties of oscillators can be exploited in oscillator design. Finally, we will show several practical examples of oscillators. |
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Jitter and Phase Noise in PLLs
We will discuss the time- and frequency-domain properties of phase locked loops. We will perform a parallel analysis of the jitter and phase noise properties of PLLs and discuss the impact of various building blocks on there properties and the output spectrum of PLLs. We will start our analysis with the discussion of first order loops and extend it to higher order loops. |
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Low-Power Crystal Oscillators
Basics of crystal oscillators. Split analysis techniques. Basics of crystals. Crystal oscillator topologies. Crystal oscillator circuit design criteria. Overview design examples. VCXO's. |
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High-Speed Synthesizers for Communications
Fractional-N synthesizers are becoming the dominant choice for communications systems for a variety of reasons that depend on the application. The need for lower phase noise, faster settling and fine frequency resolution have elevated the interest in Fractional-N synthesizers over the traditional Integer-N approaches. The lecture will focus on the fundamental advantages and challenges with using Fractional-N synthesizers in cellular, satellite and cable application. |
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Fractional-N PLLs for Frequency Synthesis
This lecture explains the extension of integer-N PLLs to fractional-N PLLs for both fine tuning resolution and in-loop VCO modulation. It presents an overview of modulus quantization noise shaping techniques, tradeoffs associated with quantization noise shaping order and PLL loop bandwidth, non-ideal effects of particular concern in fractional-N PLLs such as charge pump nonlinearities and data-dependent multi-modulus divider delays, techniques for increasing loop bandwidth, simulation techniques, and case studies of example circuits and applications. |
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Clock and Data Recovery
Architectural tradeoffs of phase-locked loop types related to differences between synchronous and packet systems. Acquisition aids of data frequency detector and synthesizer are compared. False lock caused by jitter properties of a data frequency detector is discussed in detail. Linear and bang-bang phase detectors are compared. Examples of bipolar and CMOS charge pump circuits are given. VCO requirements, especially phase noise, power supply noise rejection, and tuning linearity are explained. Brief examples of LC and Ring type of VCO are shown. Data thresholding is discussed and the magic graph paper for SNR and BER is used as a diagnostic tool. The relationship between group delay non-linearity and jitter is explained. A brief discussion of signal impairments in copper transmission media establishes the need for an equalizer to reduce intersymbol interference. Baseline wander caused by transformer coupling is explained and a zero restore circuit is shown to compensate the wander. |