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August 24-28, 2009 EPFL, Lausanne, Switzerland |
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| MONDAY, August 24 | ||
| 8:30-10:00 am | Issues in LP Design - Introduction & Basics |
Jan Rabaey,
UC Berkeley |
| 10:30-12:00 am | Issues in LP Design - Minimizing Active Power |
Jan Rabaey,
UC Berkeley |
| 1:30-3:00 pm | Issues in LP Design - Managing Leakage |
Jan Rabaey,
UC Berkeley |
| 3:30-5:00 pm | Ultra Low-Voltage Design |
Jan Rabaey,
UC Berkeley |
| TUESDAY, August 25 | ||
| 8:30-10:00 am | Interconnect-Driven Design for High-Performance Circuits |
Sachin Sapatnekar,
Univ. Minnesota |
| 10:30-12:00 am | Variation-Tolerant Design and Design for Manufacturability |
Sachin Sapatnekar,
Univ. Minnesota |
| 1:30-5:00 pm | Fundamentals of IC Reliability |
Yusuf Leblebici,
EPFL |
| WEDNESDAY, August 26 | ||
| 8:30-10:00 am | Interconnects |
Martin Rau,
Nokia Siemens Networks |
| 10:30-12:00 am | Synchronization with PLL and DLL |
Martin Rau,
Nokia Siemens Networks |
| 1:30-5:00 pm | Design for Leakage Reduction |
Christian Piguet,
CSEM |
| THURSDAY, August 27 | ||
| 8:30-12:00 am | Very High-Speed IC Design Methods |
Yusuf Leblebici,
EPFL |
| 1:30-5:00 pm | Standard Components for Digital System Integration |
Christoph Heer,
Infineon Technologies |
| FRIDAY, August 28 | ||
| 8:30-12:00 am | Custom design Techniques for High Performance |
Pat Bosshart,
Texas Instruments |
| 1:30-3:00 pm | State-of-the-Art in Digital IC Design |
Michael Smith,
MetaRam |
| 3:30-5:00 pm | Case Studies in Digital IC Design |
Michael Smith,
MetaRam |
| SATURDAY, August 29 | ||
| Optional Exams for ECTS Credits | ||