LOW-NOISE, LOW-OFFSET ANALOG IC DESIGN
AUGUST 31 - SEPTEMBER 4, 2009
EPFL, Lausanne, Switzerland
MONDAY, August 31
8:30 - 10:00 am Fundamental Noise Mechanisms in BJT Circuits Barrie Gilbert,
Analog Devices
10:30 - 12:00 am Novel Band-Gap References in All-CMOS Barrie Gilbert,
Analog Devices
1:30 - 3:00 pm Noise Topics and Tradeoffs in Practical Designs Paul Brokaw,
IDT Inc.
3:30 - 5:00 pm Noise Issues in Voltage Reference Paul Brokaw,
IDT Inc.
TUESDAY, September 1
8:30-10:00 am Bus Routing and Grounding Paul Brokaw,
IDT Inc.
10:30-12:00 am Sampled Noise Analysis Gabor Temes,
OSU
1:30 - 3:00 pm Charge Injection and Clock Feedthrough Gabor Temes,
OSU
3:30 - 5:00 pm Methodology for the Digital Autozero Calibration of Analog Circuits and Systems Maher Kayal,
EPFL
WEDNESDAY, September 2
8:30-10:00 am Low-Noise Variable and AGC Circuits Robert Blauschild,
Consultant
10:30 - 12:00 am Offset and CMRR: Random and Systematic Michiel Steyaert,
KU Leuven
1:30 - 5:00 pm CMOS Low-Noise Amplifiers Michiel Steyaert,
KU Leuven
THURSDAY, September 3
8:30-10:00 am Fundamentals on Noise Christian Enz,
CSEM
10:30 - 12:00 am Low-Frequency Noise Reduction Techniques Christian Enz,
CSEM
1:30 - 3:00 pm Noise at High-Frequency Christian Enz,
CSEM
3:30 - 5:00 pm Noise in the MOS Transistor Christian Enz,
CSEM
FRIDAY, September 4
8:30 - 12:00 am
& 1:30 - 3:00 pm
Dynamic-Offset Cancellation Techniques in CMOS Kofi Makinwa,
TU-Delft
SATURDAY, September 5
Optional Exams for ECTS Credits