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June 23-27, 2008 EPFL, Lausanne, Switzerland |
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| MONDAY, June 23 | ||
| 8:30-12:00 am | Fundamental Limitations in High-Speed Data Converters |
Marcel Pelgrom,
NXP Semiconductors |
| 1:30-5:00 pm | Flash ADCs |
Marcel Pelgrom,
NXP Semiconductors |
| TUESDAY, June 24 | ||
| 8:30-10:00 am | System Aspects of ADCs |
Marcel Pelgrom,
NXP Semiconductors |
| 10:30-12:00 am | High-Speed D/A Converters |
Michiel Steyaert,
KU Leuven |
| 1:30-3:00 pm | High-Speed Delta-Sigma Converters |
Michiel Steyaert,
KU Leuven |
| 3:30-5:00 pm | Nanometer Delta-Sigma Design |
Michiel Steyaert,
KU Leuven |
| WEDNESDAY, June 25 | ||
| 8:30-10:00 am | Overview of Pipelined ADCs |
Ian Galton,
UCSD |
| 10:30-12:00 am | Digital Background Calibration of Circuit Errors in Pipelined ADCs |
Ian Galton,
UCSD |
| 1:30-5:00 pm | Low-Voltage Pipelined and SAR ADCs |
Andrea Baschirotto,
Univ. of Milano-Bicocca & Univ. of Salento |
| THURSDAY, June 26 | ||
| 8:30-10:00 am | Case Study of a 1.2-GSa/s 15-bit DAC |
Bob Jewett,
Agilent |
| 10:30-12:00 am | Case Study of an 8-bit 20GS/s ADC |
Bob Jewett,
Agilent |
| 1:30-3:00 pm | High-Speed A/D Converters |
Klaas Bult,
Broadcom |
| 3:30-5:00 pm | Understanding and Using Power Spectral Densities for ADC Simulation, Test, and Debug |
Ian Galton,
UCSD |
| FRIDAY, June 27 | ||
| 8:30-10:00 am | High-Speed D/A Convertersn |
Klaas Bult,
Broadcom |
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10:30-12:00 am
& 1:30-3:00 pm |
Scaling Effects in Analog Design in Deep Submicron CMOS |
Klaas Bult,
Broadcom |