LOW-NOISE, LOW-OFFSET ANALOG IC DESIGN
September 1-5, 2008
EPFL, Lausanne, Switzerland
MONDAY, September 1
8:30-10:00 am Fundamental Noise Mechanisms in BJT Circuits Barrie Gilbert,
Analog Devices
10:30-12:00 am Low-Noise Variable-Gain Amplifiers Barrie Gilbert,
Analog Devices
1:30-3:00 pm Noise Topics and Tradeoffs in Practical Designs Paul Brokaw,
Analog Devices
3:30-5:00 pm Noise Issues in Voltage Reference Paul Brokaw,
Analog Devices
TUESDAY, September 2
8:30-10:00 am Bus Routing and Grounding Paul Brokaw,
Analog Devices
10:30-12:00 am Sampled Noise Analysis Gabor Temes,
OSU
1:30-5:00 pm Correlated Double Sampling Techniques Gabor Temes,
OSU
WEDNESDAY, September 3
8:30-10:00 am Charge Injection and Clock Feedthrough Gabor Temes, OSU
10:30-12:00 Am Offset and CMRR: Random and Systematic Michiel Steyaert,
KU Leuven
1:30-5:00 pm CMOS Low-Noise Amplifiers Michiel Steyaert,
KU Leuven
THURSDAY, September 4
8:30-10:00 am Methodology for the Digital Autozero Calibration of Analog Circuits and Systems Maher Kayal,
EPFL
10:30-12:00 am Low-Frequency Noise Reduction Techniques Christian Enz,
CSEM
1:30-5:00 pm High-Frequency Noise Christian Enz,
CSEM
FRIDAY, September 5
8:30-12:00 am Dynamic-Offset Cancellation Techniques in CMOS Kofi Makinwa,
TU-Delft
1:30-3:00 pm Low-Noise Variable and AGC Circuits Robert Blauschild,
Consultant