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June 30 - July 4, 2008 EPFL, Lausanne, Switzerland |
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| MONDAY, June 30 | ||
| 8:30-10:00 am | Basic Concepts of PLL Topologies |
Michiel Steyaert,
KU Leuven |
| 10:30-12:00 am | CMOS Prescalers & Advanced Loop Filters |
Michiel Steyaert,
KU Leuven |
| 1:30-5:00 am | Integrated VCOs and Synthesizers |
Michiel Steyaert,
KU Leuven |
| TUESDAY, July 1 | ||
| 8:30-12:00 am | Modeling and Design of High-Speed VCOs |
Ali Hajimiri,
Caltech |
| 1:30-3:00 pm | Jitter and Phase Noise in PLLs |
Ali Hajimiri,
Caltech |
| 3:30-5:00 pm | Clock and Data Recovery |
Lawrence DeVito,
Analog Devices |
| WEDNESDAY, July 2 | ||
| 8:30-12:00 am | Clock and Data Recovery |
Lawrence DeVito,
Analog Devices |
| 1:30-5:00 pm | Fractional-N PLLs |
Ian Galton,
UCSD |
| THURSDAY, July 3 | ||
| 8:30-12:00 am | Frequency Synthesizers in Nanometer CMOS | Bogdan Staszewski, Texas Instruments |
| 1:30-3:00 pm | Modeling for Oscillators, Frequency Synthesizers | Georges Gielen, KU Leuven |
| 3:30-5:00 pm | Phase Noise Analysis Techniques | Georges Gielen, KU Leuven |
| FRIDAY, July 4 | ||
| 8:30-12:00 am | High Speed Synthesizers for Communications | John Cowles, Analog Devices |
| 1:30-3:00 pm | Practical Examples of PLLs for Transceivers | Robert Blauschild, Consultant |