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June 23-27, 2008 EPFL, Lausanne, Switzerland |
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| MONDAY, June 23 | ||
| 8:30-10:00 am | Introduction & MOS Transistors |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Single-Stage Amplifiers, part I |
Klaas Bult,
Broadcom |
| 1:30-3:00 pm | gm/Id Methodology for MOS Device Sizing |
Maher Kayal,
EPFL |
| 3:30-5:00 pm | Basic Analog Structures Design |
Maher Kayal,
EPFL |
| TUESDAY, June 24 | ||
| 8:30-10:00 am | Single-Stage Amplifiers, part II |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Noise in MOS Transistors |
Klaas Bult,
Broadcom |
| 1:30-3:00 pm | Procedural Analog Design Using gm/Id |
Maher Kayal,
EPFL |
| 3:30-5:00 pm | Procedural Analog Design Applied to the Opamps |
Maher Kayal,
EPFL |
| WEDNESDAY, June 25 | ||
| 8:30-10:00 am | Distortion |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Basic Sub-Circuits |
Klaas Bult,
Broadcom |
| 1:30-5:00 pm | Low-Voltage Op-Amp Cells |
Rudy Eschauzier,
Maxim Integrated Products |
| THURSDAY, June 26 | ||
| 8:30-10:00 am | Gain-Boosting and Settling Behavior |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Two-Stage Amplifiers |
Klaas Bult,
Broadcom |
| 1:30-5:00 pm | High-Frequency Behavior, Feedback and Stability |
Ali Hajimiri,
Caltech |
| FRIDAY, June 27 | ||
| 8:30-12:00 am | Matching of MOS Transistors in Deep-Submicron |
Maarten Vertregt,
NXP Semiconductors |
| 1:30-3:00 am | Layout Considerations in Mixed-Signal Circuit Design |
Maarten Vertregt,
NXP Semiconductors |