|
JUNE 29 - JULY 2, 2009 EPFL, Lausanne, Switzerland |
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| MONDAY, June 29 | ||
| 8:30 - 12:00 am | Physical Device Variability |
Asen Asenov,
Univ. of Glasgow |
| 1:30 - 3:00 pm | Leakage Aware Design |
Wim Dehaene,
KU Leuven |
| 3:30 - 5:00 pm | Design for Variability in Memories |
Wim Dehaene,
KU Leuven |
| TUESDAY, June 30 | ||
| 8:30-10:00 am | Dynamic Element Matching |
Ian Galton,
UC San Diego |
|
10:30-12:00 am
& 1:30-3:00 pm |
Digital Enhancement of Analog Circuits |
Ian Galton,
UC San Diego |
| 3:30 - 5:00 pm | Layout for RF Circuits |
John Cowles,
Analog Devices |
| WEDNESDAY, July 1 | ||
| 8:30-10:00 am | Offset and CMRR: Design Strategies Towards Systematic and Random Effects |
Michiel Steyaert,
KU Leuven |
| 10:30-12:00 am | High Speed D/A Design : A Matching Story |
Michiel Steyaert,
KU Leuven |
| 1:30 - 5:00 pm | Reliability and Physical Design and Issues in Nanoscale Analog CMOS Technologies |
Lanny Lewyn,
Consultant |
| THURSDAY, July 2 | ||
| 8:30-10:00 am | Reliability and Physical Design and Issues in Nanoscale Analog CMOS Technologies (continued) |
Lanny Lewyn,
Consultant |
| 10:30 - 12:00 am | Matching of MOS Transistors in Deep-Submicron |
Maarten Vertregt,
NXP Semiconductors |
| 1:30 - 5:00 pm | Layout Considerations in Mixed-Signal Circuit Design |
Maarten Vertregt,
NXP Semiconductors |
| FRIDAY, July 3 | ||
| Optional Exams for ECTS Credits | ||