|
JUNE 29 - JULY 1, 2009 EPFL, Lausanne, Switzerland |
||
| MONDAY, June 29 | ||
| 8:30 - 12:00 am | Modeling and Design of High-Speed VCOs |
Ali Hajimiri,
Caltech |
| 1:30 - 3:00 pm | Jitter and Phase Noise in PLLs |
Ali Hajimiri,
Caltech |
| 3:30 - 5:00 pm | Low-Power Crystal Oscillators |
Michiel Steyaert,
KU Leuven |
| TUESDAY, June 30 | ||
| 8:30-10:00 am | Basic Concepts of PLL Topologies |
Michiel Steyaert,
KU Leuven |
| 10:30-12:00 am | CMOS Prescalers & Advanced Loop Filters |
Michiel Steyaert,
KU Leuven |
| 1:30-5:00 pm | Integrated VCOs and Synthesizers |
Michiel Steyaert,
KU Leuven |
| WEDNESDAY, July 1 | ||
| 8:30-12:00 am | Fractional-N PLLs |
Ian Galton,
UC San Diego |
| 1:30 - 5:00 pm | High Speed Synthesizers for Communications |
John Cowles,
Analog Devices |
| THURSDAY, July 2 | ||
| Optional Exams for ECTS Credits | ||