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June 22-26, 2009 EPFL, Lausanne, Switzerland |
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| MONDAY, June 22 | ||
| 8:30-10:00 am | gm/Id Methodology for MOS Device Sizing |
Maher Kayal,
EPFL |
| 10:30-12:00 am | Basic Analog Structures Design |
Maher Kayal,
EPFL |
| 1:30-3:00 pm | Introduction & MOS Transistors |
Klaas Bult,
Broadcom |
| 3:30-5:00 pm | Single-Stage Amplifiers, part I |
Klaas Bult,
Broadcom |
| TUESDAY, June 23 | ||
| 8:30-10:00 am | Single-Stage Amplifiers, part II |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Noise in MOS Transistors |
Klaas Bult,
Broadcom |
| 1:30-5:00 pm | Matching of MOS Transistors in Deep-Submicron |
Marcel Pelgrom,
NXP Semiconductors |
| WEDNESDAY, June 24 | ||
| 8:30-10:00 am | Distortion |
Klaas Bult,
Broadcom |
| 10:30-12:00 am | Basic Sub-Circuits |
Klaas Bult,
Broadcom |
| 1:30-5:00 pm | Layout Considerations in Mixed-Signal Circuit Design |
Marcel Pelgrom,
NXP Semiconductors |
| THURSDAY, June 25 | ||
| 8:30-10:00 am | Gain-Boosting and Settling Behavior |
Klaas Bult,
Broadcom |
| 10:00-12:00 am | Two-Stage Amplifiers |
Klaas Bult,
Broadcom |
| 1:30-5:00 pm | Low-Voltage Op-Amp Cells |
Rudy Eschauzier,
Maxim Integrated Products |
| FRIDAY, June 26 | ||
|
8:30-12:00 am
& 1:30-3:00 pm |
High-Frequency Behavior, Feedback and Stability |
Ali Hajimiri,
Caltech |
| SATURDAY, June 27 | ||
| Optional Exams for ECTS Credits | ||